1. Field of the Invention
The present invention relates to a liquid crystal display array in which one electrode of a storage capacitor within each cell is coupled to a first portion or a second portion of one gate line, thus reducing gate line delay time.
2. Description of the Related Art
A conventional thin film transistor liquid crystal display (TFT-LCD) generally comprises driving circuits and an array of cells driven thereby. The driving circuits drive a plurality of gate lines formed in parallel and a plurality of source lines formed orthogonal to the gate lines. Each cell, disposed near an intersection of one of the gate lines and one of the source lines, includes a thin film transistor (TFT) and a storage capacitor. The TFT further includes a gate coupled to a corresponding gate line and a source coupled to a corresponding source line. According to the different structures of storage capacitors, TFT-LCD arrays can be divided into two types, Cs-on-gate type and Cs-on-common type. In a Cs-on-gate array, a storage capacitor is formed between a source of a corresponding TFT and a previous gate line, that is, the reference voltage of the storage capacitor is the potential of the previous gate line. In a Cs-on-common array, a storage capacitor is formed between a source of a corresponding TFT and a common electrode, that is, the reference voltage of the storage capacitor is the potential of the common electrode.
FIG. 1 is a schematic diagram of a conventional Cs-on-common array of a TFT-LCD. The array 1 is formed by a plurality of gate lines G1n to G1n-2 and a plurality of source line D1m and D1m-1. The interlaced gate line and source line correspond to one cell, for example, the interlaced gate line G1n-1 and source line D1m-1 correspond to a cell 100. The cell 100 includes a TFT 10, a liquid capacitor Clc10, and a storage capacitor Cs10. Referring to FIG. 1, a gate of the TFT 10 is coupled to the gate line G1n-1, a source thereof is coupled to a pixel electrode 11, and a drain thereof is coupled to the source line D1m-. The storage capacitor Cs10 is formed between the pixel electrode 11 and a common electrode Vcom10. Each storage capacitor within the cells on the same row is coupled between a pixel electrode thereof and the common electrode.
FIG. 2 is a schematic diagram of a conventional Cs-on-gate array of a TFT-LCD. The array 2 is formed by a plurality of gate lines G2n to G2n-2 and a plurality of source lines D2m and D2m-1. The interlaced gate line and source line correspond to one cell, for example, the interlaced gate line G2n-1 and source line D2m-1 correspond to a cell 200. The cell 200 includes a TFT 20, a liquid capacitor Clc20, and a storage capacitor Cs20. Referring to FIG. 2, a gate of the TFT 10 is coupled to the gate line G2n-1, a source thereof is coupled to a pixel electrode 21, and a drain thereof is coupled to the source line D2m-1. The storage capacitor Cs20 is formed between the pixel electrode 21 and the gate line G2n-2. In cells on the same row, all the TFTs are coupled to the same gate line, and each storage capacitor is coupled between a pixel electrode thereof and the previous gate line.
As described above, the Cs-on-common array has an extra common electrode line, thus reducing the aperture ratio. Due to low brightness of the TFT-LCD caused by the low aperture ratio, the Cs-on-common type TFT-LCD array is less used. The Cs-on-gate type TFT-LCD array is commonly used instead. When each gate line is coupled to a plurality of storage capacitors in the Cs-on-gate array, RC effect, induced by the gate lines and the storage capacitors, causes increased in gate line delay time and degrades the capability of TFTs to charge the pixel electrodes.